The present invention relates to a semiconductor memory device such as a synchronous DRAM (Dynamic Random Access Memory), which works in synchronization with a clock signal.
Recently, a synchronous DRAM has been studied and developed as a DRAM capable of attaining high-speed data access and a large data band width (i.e., large data byte in unit of a period of time) as high as an SRAM (Static Random Access Memory). The 4M-bit and 16M-bit generation synchronous DRAMs have been already put into a market. The most remarkable feature of the synchronous DRAM is to attain data reading operation higher than that of the conventional DRAM. The synchronous DRAM can reduce a so-called column access time (t CAC): a period of time from the latching of data by a bit line controlled by a column circuit of a memory cell array to the output of the latched data to I/O pins, in comparing with the conventional device. All the operations of the synchronous DRAM are synchronism with the rising of clock signals supplied to clock signal input pins. The operations of the synchronous DRAM are quite different from that of the conventional one.
The synchronous DRAM has a power-down mode. The power-down mode is provided to reduce the power consumption of the device at a stand-by state at which a chip is not accessed. In the power-down mode, the device is controlled to stop the operations of input buffer circuits and the like in the chip in order to reduce the power consumption.
FIG. 9 shows the conventional power-down controlling section used in a synchronous DRAM and the surrounding circuit. Input buffer circuits 81 and 82 are respectively supplied with a clock signal CLK. The input buffer circuits 81 and 82 respectively output clock signals CLKIN1 and CLKIN2 to clock driving circuits 83 and 84. The clock driving circuits 83 and 84 output internal clock signals CP1 and CP2. The internal clock signals CP1 and CP2 are supplied to stages constituting a pipe-line structure.
A clock enable signal CKE for allowing the clock signal to input is supplied to an input buffer circuit 85. The input buffer circuit 85 outputs an output signal CKEIN to be supplied to a clock control circuit 86. A signal BURST is also supplied to the clock signal control circuit 86, which is a signal representing that the device is in a burst operation in which data is serially output in synchronization with the clock signal CLKIN2 output from the input buffer circuit 82 and the clock signal CLK. In response to the signal BURST, the clock control circuit 86 generates a power-down signal /PDENTR which represents that the device enters in a power-down mode. The clock control circuit 86 further generates a mask signal /CLKMSK for masking the clock signal when the power-down signal /PDENTR is generated. The mask signal /CLKMSK is supplied to the clock driving circuits 83 and 84, while, the power-down signal /PDENTR is supplied to the input buffer circuit 81 and a plurality of input buffer circuit 87 provided to the device in addition to the input buffer circuit 81.
The plurality of input buffer circuits 87 are supplied with signals such as a row address strobe signal /RAS, a column address strobe signal /CAS, a chip select signal /CS, and a write enable signal /WE. "CTRLSIG" denotes all the signals input into the input buffer circuits 87. An output signal COMIN of each of the input buffer circuits 87 is supplied to a command decoder 88. Similarly to the signal CTRLSIG, "COMIN" also denotes all the signals output from the input buffer circuits 87 (i.e., the raw address strobe signal /RAS, the column address strobe signal /CAS, the chip select signal /CS, the write enable signal /WE and the like). A command decoder 88 decodes the row address strobe signal /RAS, the column address strobe signal /CAS, and the like, and generate a command COMDEC to instruct various types of operation such as write operation, read operation, or the like which corresponds to the decoded signal. The generated command COMDEC is supplied to a clocked inverter circuit 91 driven by the internal clock signals CP1 and /CP1, through a clocked inverter circuit 89 also driven by the internal clock signal CP1 and /CP1 and an inverter circuit 90. An output signal COMLTC of the clocked inverter circuit 91 is supplied to an internal circuit (not shown).
FIG. 10 shows the constitution of the input buffer circuit 81. The input buffer circuit 81 includes a current mirror circuit CM1 constituted of P-channel MOS transistors (hereinafter referred to as "PMOS transistors") 81a, 81b, and 81c, N-channel MOS transistors (hereinafter referred to as "NMOS transistors") 81d, 81e, and 81f. A gate of the PMOS transistor 81a is applied with a ground potential Vss, and a gate of the NMOS transistor 81d is applied with a reference potential Vref. Similarly, a gate of the NMOS transistor 81e is supplied with a clock signal CLK, and a gate of the NMOS transistor 81f is supplied with the power-down signal /PDENTR.
Between a connection node N1 connecting the PMOS transistor 81c with the NMOS transistor 81e and the power supply Vcc, a PMOS transistor 81g is arranged to connect them. A gate of the PMOS transistor 81g is supplied with the power-down signal /PDENTR.
The connection node N1 is further connected to one input terminal of a NAND circuit 81i constituting a flip-flop circuit 81h. Between one input terminal and the other terminal of a NAND circuit 81j constituting the flip-flop circuit 81h together with the NAND circuit 81i, a plurality (three, for example) of inverter circuits constituting a delay circuit 81k are connected in series. An output terminal of the NAND circuit 81i is connected to inverter circuits 81l and 81m in series, and a signal CLKIN1 is output from an output terminal of the inverter circuit 81m.
FIG. 11 shows the constitution of the clock driving circuit 83. The clock driving circuit 83 is constituted from a NAND circuit 83a supplied with the signal CLKIN1 and the mask signal /CLKMSK and an inverter circuit 83b connected to an output terminal of the NAND circuit 83a. The internal clock signal CP1 is output from an output terminal of the inverter circuit 83b.
FIG. 12 shows the constitution of the input buffer circuit 82, and FIG. 13 shows the clock driving circuit 84. The input buffer circuit 82 has substantially the same constitution as that of the input buffer circuit 81. The clock driving circuit 84 also has substantially the same constitution as that of the clock driving circuit 83. Accordingly, like reference numerals are used to designate like portions respectively having the same function as those in FIGS. 10 and 12 for simplicity of illustration, and only different portions will be described below.
Unlike in the input buffer circuit 81, the gate of the NMOS transistor 81f is applied with the power supply voltage Vcc, and the PMOS transistor 81g shown in FIG. 10 is not used in the input buffer circuit 82 shown in FIG. 12. The inverter circuit 81m outputs a signal CLKIN2.
In the clock driving circuit 84 shown in FIG. 13, one of input terminals of the NAND circuit 83a is supplied with the signal CLKIN2, and the inverter circuit 83b outputs an internal clock signal CP2.
FIG. 14 shows the circuit constitution of the input buffer circuit 87. The input buffer 87 includes a current mirror circuit CM2 constituted from PMOS transistors 87a, 87b, and 87c, and NMOS transistors 87d, 87e, and 87f. A gate of the PMOS transistor 87a is applied with the ground potential Vss, and a gate of the NMOS transistor 87d is applied with the reference potential Vref. Similarly, a gate of the NMOS transistor 87e is supplied with the signal CTRLSIG, and a gate of the NMOS transistor 87f is supplied with the power-down signal /PDENTR.
Between a connection node N2 connecting the PMOS transistor 87c with the NMOS transistor 87e and a power supply Vcc, a PMOS transistor 87g is arranged to be connected thereto. A gate of the PMOS transistor 87g is supplied with the power-down signal /PDENTR.
Three inverter circuits 87h, 87i, and 87j are connected in series to a connection node N2, and a signal COMIN is output from the output terminal of an inverter circuit 87j.
FIG. 15 shows the constitution of the input buffer circuit 85. The input buffer circuit has substantially the same constitution as that of the input buffer circuit 87. Accordingly, the same elements are denoted by the same reference numerals, and only the different elements will be described below.
Unlike in the input buffer circuit 87, the gate of the NMOS transistor 87f shown in FIG. 15 is applied with the power supply voltage Vcc, and the PMOS transistor 87g is not used to be connected with the connection node N2. Further, the inverter circuit 87j outputs a signal CKEIN.
FIG. 16 shows the constitution of the clock control circuit 86. In this circuit, clocked inverter circuits 86a, 86c, and 86g, and inverter circuits 86b, 86d, 86f, 86h, and 86i are connected in series as shown in the drawing. The inverter circuit 86i outputs the mask signal /CLKMSK from the output terminal. The inverter circuit 86d is connected to the clocked inverter circuit 86e in parallel to constitute a latch circuit. The clocked inverter circuits 86a, 86c, 86e, and 86g are respectively driven by the signal CLKIN2 or the inverted signal /CLKIN2 obtained by inverting the signal CLKIN2. An output terminal of the clocked inverter circuit 86g is connected to one of input terminals of a NOR circuit 86i. The other input terminal of the NOR circuit 86i is supplied with the signal BURST, and an output terminal of the NOR circuit 86i is connected to an input terminal of the inverter circuit 86k. From an output terminal of the inverter circuit 86k, the power-down signal /PDENTR is output.
FIG. 17 shows the operations of the circuits shown in FIGS. 9, 10, 11, 12, 13, 14, 15, and 16. With the circuit constitutions as described above, when a clock enable signal CKE supplied to the input buffer circuit 85 is set at a low level, the signal CKEIN as the output of the input buffer circuit 85 is also set at a low level. A power-down signal /PDENTR is thus output from the clock control circuit 86 to set the device in the power-down mode. The operations of the input buffer circuits 81 and 87 are stopped upon receiving the power-down signal /PDENTR to reduce the power consumption. In this time, the mask signal /CLKMSK is output from the clock control circuit 86 to mask the internal clock signals CP1 and CP2 output from the clock driving circuits 83 and 84.
Contrarily, when the clock enable signal CKE to be input into the input buffer circuit 85 is set at a high level in the power-down mode, the input buffer circuit 85 constantly set at a active state outputs the signal CKEIN. The input buffer circuit 82 is also constantly set at an active state. The clock control circuit 86 thus takes the signal CKEIN output from the input buffer circuit 85 upon receiving the signal CLKIN2 supplied from the input buffer circuit 82 and the inverted signal /CLKIN2. In accordance with the taken signal CKEIN, the clock control circuit 86 sets the power-down signal /PDENTR and the mask signal /CLKMSK at a high level. The power-down mode is released thereby, and the input buffer circuits 81 and 87 and the like are set at an active state to execute operation such as decoding and latching of a command.
As described above, with the above-mentioned conventional constitution, the power-down mode is released upon receiving the clock signal CLK externally supplied when the clock enable signal CKE is set at a high level. In other words, in order to release the power-down mode to activate the circuits, the conventional constitution necessarily needs one external clock signal CLK after the clock enable signal CKE is set at a high level. More specifically, as shown in FIG. 17, the internal clock signal CP1 is never output unless a clock signal CLKn+1 next to the clock signal CLKn for releasing the power-down mode is output. In accordance with the internal clock signal CP1, the clocked circuit 91 receives a command. Accordingly, a period of time necessarily intervenes between the releasing of the power-down mode and the latching of the command.
Further, the period of time for releasing the power-down mode depends on a cycle time. Accordingly, if the cycle time is elongated, the period of time from the setting of the clock enable signal CKE at a high level to the releasing of the power-down mode is elongated naturally. Therefore, with a long cycle time, a period of time from the releasing of the power-down mode to the latching of the command is further elongated, in comparing with the normal case.
In addition, with the above-mentioned constitution, the signal CLKIN2 generated from the clock signal CLK is necessary to output in order to release the power-down mode, and thus the input buffer circuit 82 for generating the signal CLKIN2 needs to be constantly activated. Accordingly, the input buffer circuit for receiving a clock signal must comprise two circuits: an input buffer circuit set at a non-activate state in the power-down mode; and an input buffer circuit set at an activate state in the power-down mode. The input buffer circuit for receiving the clock signal is thus inevitably complicated in structure. Further, the device is provided with a plurality of input buffer circuits activated in the power-down mode, and thus the power consumption will inevitably increase.